Renesas Electronics /R7FA6M3AH /EPTPC /MITSELR

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Interpret as MITSELR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)MINTEN0 0 (0)MINTEN1 0 (0)MINTEN2 0 (0)MINTEN3 0 (0)MINTEN4 0 (0)MINTEN5

MINTEN5=0, MINTEN3=0, MINTEN0=0, MINTEN2=0, MINTEN4=0, MINTEN1=0

Description

MINT Interrupt Request Timer Select Register

Fields

MINTEN0

Pulse Output Timer 0 MINT Interrupt Output Enable

0 (0): Output of rising edges by pulse output timer 0 is not reflected by the MIESR.CYC0 flag as a MINT interrupt source.

1 (1): Output of rising edges by pulse output timer 0 is reflected by the MIESR.CYC0 flag as a MINT interrupt source.

MINTEN1

Pulse Output Timer 1 MINT Interrupt Output Enable

0 (0): Output of rising edges by pulse output timer 1 is not reflected by the MIESR.CYC1 flag as a MINT interrupt source.

1 (1): Output of rising edges by pulse output timer 1 is reflected by the MIESR.CYC1 flag as a MINT interrupt source.

MINTEN2

Pulse Output Timer 2 MINT Interrupt Output Enable

0 (0): Output of rising edges by pulse output timer 2 is not reflected by the MIESR.CYC2 flag as a MINT interrupt source.

1 (1): Output of rising edges by pulse output timer 2 is reflected by the MIESR.CYC2 flag as a MINT interrupt source.

MINTEN3

Pulse Output Timer 3 MINT Interrupt Output Enable

0 (0): Output of rising edges by pulse output timer 3 is not reflected by the MIESR.CYC3 flag as a MINT interrupt source.

1 (1): Output of rising edges by pulse output timer 3 is reflected by the MIESR.CYC3 flag as a MINT interrupt source.

MINTEN4

Pulse Output Timer 4 MINT Interrupt Output Enable

0 (0): Output of rising edges by pulse output timer 4 is not reflected by the MIESR.CYC4 flag as a MINT interrupt source.

1 (1): Output of rising edges by pulse output timer 4 is reflected by the MIESR.CYC4 flag as a MINT interrupt source.

MINTEN5

Pulse Output Timer 5 MINT Interrupt Output Enable

0 (0): Output of rising edges by pulse output timer 5 is not reflected by the MIESR.CYC5 flag as a MINT interrupt source.

1 (1): Output of rising edges by pulse output timer 5 is reflected by the MIESR.CYC5 flag as a MINT interrupt source.

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